This invention relates to the alignment of a received clock signal with a received data signal. More particularly, this invention relates to such alignment on a programmable logic device.
It is almost axiomatic that digital systems are clocked. For a clock of period T, the clock signal is typically a series of square (or rectangular) pulses of durations T/2, separated by zero-amplitude intervals of durations T/2. Such a clock has a rate or frequency of 1/T. The clock is used to time data signals, with each data pulse having a duration T. However, there is no reason why consecutive data pulses need be separated by zero-amplitude intervals. Therefore, two or more (n) consecutive data pulses can be transmitted as a single continuous “high” signal of duration nT. In each clock period T, one data pulse can be transmitted. Thus, the data rate of the system is the same as that of the clock rate. In a double data rate system, data is sampled on both rising and falling clock edges, resulting in a data rate twice that of the clock rate, with each data pulse having a duration T/2.
Because any particular data pulse can be either high (“1”) or low (“0”), a train of unknown data pulses is commonly represented by two superposed waves, with the edges of the pulses are not purely vertical, so that the progression of pulses is distinctly visible. Each possible data position thus is shown as both high and low, signifying that either value is possible in a stream of actual data. Because the edges representing the pulse transitions in such a representation are not purely vertical, the intersecting inclined lines give each pulse position the appearance of an eye, and each pulse position is therefore referred to as a “data eye.”
When sampling data, it is best that the sampling occur as close as possible to the center of the data eye, as far as possible from the transitions, because sampling during a transition could provide a false reading of the data. When the clock must be recovered from the data, clock recovery errors, in combination with other errors such as process and temperature variations as well as trace length variations, makes centering the sampling time in the data eye—“eye centering”—difficult or unreliable. Any such problems are compounded in a programmable logic device, where the circuit paths, as well as the clock recovery circuitry, differ from one user logic design to the next.
Clock data alignment is considered relatively easy when the clock is sent along with the data. However, in applications where the circuit path may vary, particularly in the case of programmable logic devices, alignment of the received data and the received clock cannot be assured. In particular, if one clock is sent in conjunction with more than one data signal, the clock as well as each of the data signals potentially is subject to a different delay, and continued alignment of the received clock with any one received data signal cannot be assured. Solutions to these problems are available, utilizing loop circuits—e.g., phase-locked loops or delay-locked loops—to align the clock with the data. However, such circuits continue to run after data alignment, consuming power unnecessarily where misalignment is the result only of circuit path differences or other factors that remain constant during operation.
It would be desirable to be able to provide a method and circuitry for reliable eye centering with reduced power consumption, and even in a programmable logic device.